Senior RF IC Design Engineer | Last Mile Semiconductor GmbH: Senior RF IC Design Engineer (m/w/x)

Last Mile Semiconductor GmbH

Dresden, Sachsen, Deutschland
Published Feb 15, 2026
Full-time
No information

Job Summary

As a Senior RF IC Design Engineer at Last Mile Semiconductor, you will play a pivotal role in developing next-generation NR+ microchips for non-cellular 5G applications. Your daily responsibilities include designing high-frequency integrated circuits using deep-submicron CMOS technology, specifically 22FDX FD-SOI. You will lead the entire product development lifecycle, from initial concept and block-level specification to top-level simulations, pre-tapeout verification, and post-silicon characterization. This role requires close collaboration with layout and system teams to ensure design optimization and successful IP validation. What makes this position unique is the opportunity to work in a high-growth startup environment in the heart of 'Silicon Saxony' (Dresden), contributing to a revolutionary wireless standard that enables massive IoT use cases. You will have significant creative freedom and direct influence on the development of a new class of wireless communication technology within an international and innovative team.

Required Skills

Education

Degree in Electrical Engineering, Microelectronics, or a related technical field.

Experience

  • Several years of professional experience in RF or Analog IC Design within the semiconductor industry
  • Extensive experience across the full RFIC product development lifecycle from concept to mass production
  • Proven track record of successful tape-outs for specific functional blocks
  • Professional experience with modern CMOS process technologies, ideally 22FDX
  • Experience in translating system specifications into concrete circuit requirements
  • Practical experience in laboratory RF measurements and silicon characterization

Languages

Not specified

Additional

  • Location: Dresden, Germany. Full-time permanent position. Requires expertise in deep-submicron CMOS and RF-optimized layout.