Staff/Principal ASIC Design Engineer | Last Mile Semiconductor GmbH: Staff/ Principal ASIC Design Engineer (m/w/x)

Last Mile Semiconductor GmbH

Dresden, Sachsen, Deutschland
Published Feb 9, 2026
Full-time
No information

Job Summary

This senior-level role involves providing technical leadership for the Digital Design team, focusing on coaching, mentoring, and fostering the professional growth of engineers. The Staff/Principal ASIC Design Engineer will take ownership of the Digital and SoC architecture, playing a crucial role in defining and optimizing the RF System-on-Chip architecture. Key responsibilities include RTL design for complex digital blocks, system-level integration, and ensuring quality control through design reviews. The role acts as a critical interface between Analog/RF Design, System Architecture, Firmware, and Product Management, ensuring effective communication and technically sound alignments. Furthermore, the position contributes to technical strategy by evaluating new technologies, defining design and verification methodologies, and supporting chip bring-up, qualification, and ramp-up. This is an attractive opportunity for an experienced ASIC professional to drive technical excellence in a dynamic semiconductor startup focused on developing cost-effective, ultra-low-power 5G cellular chipsets for massive IoT applications.

Required Skills

Education

Degree in Electrical Engineering, Microelectronics, Computer Science, or a comparable field

Experience

  • 12–15+ years of professional experience in ASIC Digital Design
  • Several years in a Senior, Staff, or Principal role (ideally)
  • Excellent knowledge of RTL Design and SoC integration of complex Mixed-Signal Systems
  • Strong experience in conceiving Chip and Subsystem Architectures
  • Proven ability to technically lead teams and provide mentoring

Languages

English (Fluent)

Additional

  • Not specified