Staff/Principal ASIC Design Engineer | Last Mile Semiconductor GmbH: Staff/ Principal ASIC Design Engineer (m/w/x)

Job Summary

This senior technical role involves providing technical leadership, coaching, and mentoring to the Digital Design team, ensuring their continuous development and maximizing team potential. The Staff/Principal Engineer will assume ownership of the Digital and System-on-Chip (SoC) architecture, driving its definition, optimization, and evolution for next-generation RF chips. Key day-to-day tasks include complex RTL design and system-level integration, performing design reviews, and maintaining stringent quality control. The position requires acting as a critical technical interface across Analog/RF Design, System Architecture, Firmware, and Product Management teams. Candidates must possess 12–15+ years of experience in ASIC Digital Design, expertise in RTL (SystemVerilog, VHDL), and deep knowledge of modern verification methods. This is an attractive opportunity to contribute strategically to the development of a revolutionary, low-power 5G cellular chipset within a dynamic semiconductor startup in Dresden.