Senior ASIC Design Engineer | Last Mile Semiconductor GmbH: Senior ASIC Design Engineer (m/w/x)

Job Summary

This Senior ASIC Design Engineer role involves crucial contributions to the definition and advancement of RF System-on-Chip (SoC) architectures, specifically focusing on next-generation 5G cellular chipsets for massive IoT applications. The engineer will be responsible for the RTL design of digital blocks, system-level integration, and close collaboration with Analog/RF teams to realize highly integrated RF ASICs. Key responsibilities include developing and executing functional verification at both block and chip levels, supporting qualification, testing, and chip ramp-up, and documenting development processes. Candidates need a degree in Electrical Engineering or Microelectronics, deep knowledge of ASIC Digital Design and SoC integration, and proficiency in hardware description languages like SystemVerilog, Verilog, or VHDL. The position offers high levels of autonomy, excellent development opportunities, and the chance to work in an international, supportive team environment in Dresden, Germany.