Senior ASIC Design Engineer | Last Mile Semiconductor GmbH: Senior ASIC Design Engineer (m/w/x)

Job Summary

This Senior ASIC Design Engineer role involves contributing to the definition and continuous development of the company's RF System-on-Chip (SoC) architecture. The successful candidate will take responsibility for the RTL design of digital blocks and their seamless integration at the system level. A key aspect of the job is close collaboration with the Analog/RF team to realize highly integrated RF ASICs. Day-to-day tasks include developing and executing functional verification at both block and chip levels, utilizing modern verification methodologies such as UVM, and supporting the chips through qualification, testing, and ramp-up phases. The role requires a degree in Electrical Engineering or Microelectronics, profound knowledge of ASIC Digital Design and SoC integration, and proficiency in hardware description languages like SystemVerilog, Verilog, or VHDL. Working in an international team, good English skills are essential for success in this innovative semiconductor startup focused on 5G cellular chipsets for IoT.