Staff/Principal ASIC Design Engineer | Last Mile Semiconductor GmbH: Staff/ Principal ASIC Design Engineer (m/w/x)

Job Summary

This role is for a highly experienced Staff or Principal ASIC Design Engineer to provide technical leadership for the Digital Design team within a semiconductor startup focused on 5G non-mobile IoT chipsets. Day-to-day responsibilities include leading, coaching, and mentoring digital design engineers, taking ownership of the Digital and System-on-Chip (SoC) architecture, and being responsible for the RTL design and system-level integration of complex digital blocks. The engineer will act as a critical interface between Analog/RF Design, System Architecture, Firmware, and Product Management, ensuring effective communication and technically sound decisions. Key requirements include 12–15+ years of professional experience in ASIC Digital Design, excellent knowledge of RTL design (SystemVerilog, Verilog, or VHDL), and deep understanding of modern verification methodologies. This position is attractive due to its high level of responsibility, strategic technical contribution to a revolutionary 5G chipset, and the opportunity to shape the development and quality processes within a fast-growing international team in Dresden.