System on Chip (SoC) Verification Engineer | System on Chip (SoC) Verification Engineer (all genders)

Job Summary

This role is for a System on Chip (SoC) Verification Engineer to join the Fraunhofer Institute for Integrated Circuits IIS in Erlangen, Germany. You will be instrumental in pre-silicon RTL verification of block and top-level SoC designs, specifically utilizing RISC-V architecture. Your day-to-day will involve developing and maintaining reusable testbenches, creating smart test cases tailored to RISC-V SoCs, analyzing coverage models, and debugging test failures. The ideal candidate will have a solid understanding of digital logic design, RISC-V-based SoC architecture, and proven experience with SystemVerilog and UVM-based verification environments. This position offers the opportunity to contribute to cutting-edge research in microelectronics and chip design, working within an international team focused on developing trusted and energy-efficient high-speed ICs for Europe.