Senior IC Layout Engineer | Last Mile Semiconductor GmbH: Senior Layout Engineer (m/w/x)

Job Summary

As a Senior Layout Engineer at Last Mile Semiconductor, you will play a critical role in the physical design of high-performance RF and Mixed-Signal integrated circuits. Based in Dresden, you will take ownership of the entire layout process, from initial floorplanning to successful tape-out. You will collaborate closely with cross-functional RF, Analog, and Digital teams to optimize performance, manage parasitic effects, and ensure high yield for our cutting-edge CMOS and FD-SOI based SoCs. Key responsibilities include executing complex layout tasks, performing verification (DRC, LVS, ERC), and contributing to the refinement of layout methodologies. This is an exciting opportunity to join a deep-tech startup at the forefront of the DECT NR+ wireless standard, offering high levels of autonomy, a collaborative international environment, and the chance to shape the next generation of energy-efficient IoT connectivity solutions.