Senior Layout Engineer | Last Mile Semiconductor GmbH: Senior Layout Engineer (m/w/x)

Last Mile Semiconductor GmbH

Dresden, Sachsen, Deutschland
Published Mar 31, 2026
Full-time
No information

Job Summary

As a Senior Layout Engineer at Last Mile Semiconductor, a Dresden-based deep-tech startup, you will play a pivotal role in developing next-generation energy-efficient wireless connectivity solutions. Your day-to-day responsibilities involve the physical design of highly integrated RF and Mixed-Signal ICs, managing the process from initial floorplanning to successful tape-out. You will implement high-performance layout techniques such as matching, symmetry, and shielding while performing rigorous verification using DRC, LVS, and ERC tools. This role is ideal for an expert in CMOS and FD-SOI technologies who enjoys working in a collaborative, interdisciplinary environment. The position offers a unique opportunity to work on the cutting edge of DECT NR+ and IoT standards within 'Silicon Saxony'. You will benefit from a flexible work environment, including hybrid options, flat hierarchies, and a culture that values technical innovation and professional growth.

Required Skills

Education

University degree in Electrical Engineering, Microelectronics, or a comparable field of study.

Experience

  • Several years of professional experience in IC Layout focusing on Analog, RF, or Mixed-Signal designs
  • Extensive experience with industrial tape-out flows and foundry interfaces
  • Proven track record using Cadence layout tools and verification workflows
  • Professional experience with advanced technology nodes such as 22FDX
  • Experience in managing layout parasitics and their impact on circuit performance

Languages

German (Basic)English (Fluent)

Additional

  • The role is based in Dresden, Germany. It requires a structured and quality-oriented way of working. One regular home office day per week is provided with additional mobile work options by arrangement.