Senior Staff Engineer, Digital Verification | Ingenieur/in - Elektrotechnik

Job Summary

This role seeks a highly experienced Senior Staff Engineer specializing in Digital Verification within the Research & Development team, focusing on Mixed Signal designs. The professional will be responsible for creating and defining comprehensive verification plans and developing advanced verification environments using SystemVerilog and Universal Verification Methodology (UVM) with a Constrained Random approach. Day-to-day tasks include executing tests on RTL and gate-level, debugging design and verification issues, and closely collaborating with analog and digital designers. A key aspect of this position involves leadership and coordination of other verification engineers, mentoring junior staff, and driving innovation projects to enhance existing methodologies and flows. The ideal candidate must possess a university degree in Electrical Engineering or Computer Science and over six years of relevant experience, coupled with excellent expertise in SystemVerilog, UVM, and industry-standard verification tools.