Mixed-Signal ASIC Layout Engineer | Engineer für Mixed-Signal-ASIC-Layout (m/w/d)

Job Summary

This role involves the creation and optimization of physical layouts for RF and Analog components, specifically utilizing SiGe-BiCMOS technology. The Layout Engineer will be responsible for executing the full verification process, including Design Rule Check (DRC) and Layout Versus Schematic (LVS), using industry-standard tools like Cadence Assura/PVS. A key part of the job is collaborating closely with RF-IC Design and System teams on floor planning and automating development workflows using scripting languages like Skill or Python. Candidates must possess multi-year experience in custom RF and Analog layout, deep knowledge of SiGe-BiCMOS technologies, and expertise in critical layout methods such as parasitic reduction and high-frequency wiring. This fixed-term position is ideal for an Electrical Engineering graduate seeking to drive innovation in high-frequency semiconductor development.