Static Timing Analysis (STA) Engineer | STA Engineer (m/f/d) #200653786

Job Summary

As an STA Engineer, you will play a critical role in the semiconductor design lifecycle by ensuring full chip timing and noise convergence. Your day-to-day activities involve developing automated block and full-chip level signoff flows, enabling hierarchical timing flows, and performing power optimizations. You will act as a central technical bridge, collaborating closely with DFT, Top Level PNR, PHY, and architecture teams to drive custom IP integration and timing check flows. The role requires generating block-level budgets and ensuring correlation with the full chip for high-quality tape-outs. This position is particularly attractive for engineers who enjoy complex problem-solving in high-performance silicon design, offering the chance to work on sophisticated hierarchical design approaches and cutting-edge signoff methodologies within a highly collaborative environment.