SOC Physical Design Engineer | SOC Physical Design Engineer (m/f/d) #200642449
Apple Technology Engineering B.V. & Co. KG
Job Summary
This role is for an experienced Physical Design Engineer to join a world-class team focused on delivering high-performance, deep sub-micron System-on-Chip (SoC) products for Apple. The engineer will own the large-scale SoC physical design cycle from netlist to tape-out, ensuring adherence to schedule and design goals. Key responsibilities include block-level Place and Route (PnR), floor-planning, clock and power distribution, static timing closure, and comprehensive power and noise analysis (EM/IR-Drop/Xtalk). The ideal candidate must possess a Master's degree in Electrical Engineering (or equivalent experience) and extensive hands-on expertise with industry-standard PnR tools (Synopsys/Cadence). Success in this role requires a strong track record of recent successful tape-outs, proficiency in scripting (Perl, TCL, Make), and excellent communication skills for collaboration within a dynamic, multi-cultural environment.
Required Skills
Education
Master of Science in Electrical Engineering (MSEE) or equivalent strong experience
Experience
- Years of hands-on experience with Place & Route (PnR) tools (Synopsys / Cadence)
- Strong track record with recent successful tape-outs in deep sub-micron technology
- Experience with large SoC designs (>20M gates) with frequencies in excess of 1GHZ
- Professional experience with SoC practices (multiple voltage/clock domains, mixed-signal IP integration)
Languages
Additional
- Not specified
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