Mixed Signal ASIC Layout Engineer | Mixed Signal ASIC Layout Engineer (m/w/d)

Job Summary

This role involves the physical design and verification of high-frequency (HF)/Analog Silicon Germanium (SiGe) BiCMOS circuit modules, working closely with the design engineering team. Key responsibilities include utilizing Cadence Virtuoso XL for block-level layout, executing the full verification process (DRC, LVS) using Cadence Assura/PVS tools, and coordinating floorplanning with the RF-IC design and RF-system teams. The ideal candidate possesses a degree in Electrical Engineering and several years of experience in RF/Analog layout, coupled with deep knowledge of SiGe-BiCMOS processes. Expertise in layout techniques for device matching, parasitic effect reduction, RF shielding, and optimal high-frequency routing is crucial. This position offers an opportunity to actively contribute to innovative future technologies within a dynamic, growing company, requiring strong German communication skills for effective interaction with German-speaking clients and project teams.