Senior ASIC Design Engineer | Last Mile Semiconductor GmbH: Senior ASIC Design Engineer (m/w/x)

Job Summary

The Senior ASIC Design Engineer will play a pivotal role in defining and advancing the RF System-on-Chip (SoC) architecture for a semiconductor startup focused on next-generation, non-mobile 5G cellular chipsets enabling massive IoT applications. Day-to-day responsibilities include leading the RTL design of digital blocks, integrating them at the system level, and collaborating closely with the Analog/RF team to realize highly integrated RF ASICs. The role also encompasses developing and executing functional verification at both block and chip levels, supporting chip qualification, testing, and ramp-up, and ensuring thorough documentation of the development process. This position requires a background in electrical engineering or microelectronics, deep expertise in ASIC Digital Design, particularly SoC integration, and proficiency in hardware description languages like SystemVerilog, Verilog, or VHDL. The ideal candidate will thrive in an international, fast-paced environment and contribute to building cost-effective, ultra-low power connectivity solutions.