Functional Digital Verification Engineer | Ingenieur/in - Elektrotechnik

Job Summary

This role seeks an experienced Functional Digital Verification Engineer to join the Research & Development team, driving groundbreaking projects in cutting-edge technology. Day-to-day responsibilities include creating and defining comprehensive verification plans for Mixed Signal designs. A core part of the job involves building and enhancing verification environments using advanced methodologies like SystemVerilog, UVM, and Constrained Random approaches. You will execute rigorous tests on RTL and gate-level, requiring strong debugging skills to resolve issues in both the design and verification environments. Success requires a university degree in a relevant technical field such as Electrical Engineering or Computer Science, and ideally 3-5 years of related experience, coupled with expert knowledge of UVM and RTL design. The position demands a conscientious, independent, and collaborative team player who can maintain high quality standards, cooperate closely with analog and digital designers, and mentor junior colleagues. This is a permanent, full-time position offering the opportunity to merge technical expertise with creativity.