Senior ASIC Design Engineer | Last Mile Semiconductor GmbH: Senior ASIC Design Engineer (m/w/x)

Job Summary

This Senior ASIC Design Engineer role is pivotal in defining and advancing the RF System-on-Chip (SoC) architecture for a semiconductor startup specializing in non-mobile 5G cellular chipsets. Daily responsibilities include taking ownership of the Register-Transfer Level (RTL) design for digital blocks, integrating these blocks at the system level, and working closely with Analog and RF teams to realize highly integrated RF ASICs. The engineer will also be responsible for developing and executing functional verification at both block and chip levels, documenting development processes, and supporting chip qualification and production ramp-up. Candidates must possess a degree in Electrical Engineering or Microelectronics, deep knowledge of ASIC Digital Design and SoC integration, and proficiency in hardware description languages like SystemVerilog, Verilog, or VHDL. This position offers high personal responsibility, excellent development opportunities, and the chance to contribute to cutting-edge 5G NR+ technology within a supportive, international team environment in Dresden, Germany.