Senior Functional Verification Engineer | Senior Functional Verification Engineer (m/f/d)

Job Summary

This Senior Functional Verification Engineer role is critical to delivering high-quality, high-performing on-chip network (NoC) IP solutions. The successful candidate will be responsible for developing and maintaining robust verification environments using UVM SystemVerilog, elaborating product specifications, and creating comprehensive functional verification plans. Day-to-day tasks include designing and improving verification test benches, debugging identified errors, and ensuring coverage closure by monitoring daily regression runs. This position requires a minimum of five years of relevant work experience, expertise in UVM SystemVerilog and SystemVerilog Assertions, and a degree in Electrical Engineering, Computer Engineering, or a related field. The role emphasizes strong collaboration with digital design teams, a focus on design quality, and excellent English communication skills, offering attractive benefits like flexible working hours and mobile work options.