Package Design Engineer | Package Design Engineer

Kandou Bus SA

St-Sulpice VD, VD, Switzerland
Published Nov 28, 2025
Full-time
Permanent

Job Summary

This role is for a passionate and accomplished Package Design Engineer to join Kandou, an innovative leader in high-speed, energy-efficient chip-chip link solutions within the semiconductor industry. You will be responsible for completing all package design activities, ensuring compliance with design rules through review processes with Assembly subcontractors, and closely collaborating with IC layout engineers. A key focus is verifying electrical characteristics using specialized software tools (Cadence, Ansys) and ensuring cost-effective methodologies are incorporated into BGA substrate and LF designs. You will provide support and guidance for assembly/package related activities and present detailed weekly progress reports to cross-functional teams. This position is attractive as it offers the chance to be part of a high-tech scale-up, challenging the status quo, and working across multi-functional groups including product design and engineering to drive the future evolution of electronics. Success requires strong technical expertise in IC Package Design and excellent communication skills to manage external assembly partners effectively.

Required Skills

Education

Not specified

Experience

  • Minimum 5 years experience in IC Package Design using Cadence APD / SIP.
  • Hands-on experience utilizing Cadence (Virtuoso, Extract IM, Power DC) and Ansys (SiWave, Q3D) or similar simulation tools.
  • Strong knowledge of various Electronic IC Packaging technology.
  • Basic understanding of Thermal and Mechanical behaviour of IC Packages.

Languages

English (Fluent)

Additional

  • Requires strong interpersonal and communication skills, including networking, negotiation, and influencing abilities. Must be adept at managing communication with assembly subcontractors and proficient in estimating timescales to meet tight deadlines.