Principal Engineer Digital Verification | Principal Engineer Digital Verification (f/m/div)

Job Summary

This role is for a Principal Engineer in Digital Verification, focusing on leading IP-level verification efforts. The successful candidate will be responsible for developing advanced System Verilog-UVM testbenches, debugging complex digital issues, and defining robust functional coverage models. The position involves close collaboration with a passionate team, taking ownership of end-to-end verification processes, and contributing to innovative solutions within a dynamic and supportive environment. It offers an opportunity to drive technical excellence and ensure the quality of digital designs.